Signal Receiving Circuit and Signal Input Detection Circuit

ABSTRACT

In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits  2   a  to  2   n  for receiving clock signals S 1 - c  to SN-c included in N channels of signals S 1  to SN. Each of the input detection circuits  2   a  to  2   n  detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. If one of the input detection circuits  2   a  to  2   n  detects the input of the signal of the corresponding channel, the selection circuit  3  selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit  4 , the serial/parallel conversion circuit  5 , etc., which are shared by N channels. Therefore, there is needed only one each of input processing circuits such as the serial/parallel conversion circuit, thus saving the stand-by current for these input processing circuits.

TECHNICAL FIELD

The present invention relates to a signal receiving circuit forreceiving signals from a plurality of channels and performing apredetermined input signal process on these signals.

BACKGROUND ART

In recent years, video display devices of rapidly growing popularity,such as plasma displays and liquid crystal displays, are increasinglyrequired to have a plurality of signal receiving interfaces, as more andmore video signal supplying devices, such as DVD players, set top boxesbeing digital broadcast receivers or personal computers, are connectedthereto, so that a plurality of such video signal supplying devices canbe connected to a video display device.

Patent Document 1 discloses a conventional configuration of a videointerface device of a single video display device for receiving videosignals from a plurality of video signal supplying devices as describedabove. An important part of the video interface disclosed in PatentDocument 1 will be described with reference to FIG. 5. A video interfacedevice A includes three input signal processing sections C-1, C-2 andC-3 for receiving three channels of video signals B-1, B-2 and B-3 fromthree video supplying devices (not shown), and a video selection circuitE for selecting a video signal of one channel from among video signalsD-1, D-2 and D-3 obtained by performing an input process by the threeinput signal processing sections C-1 to C-3. The video selection circuitE receives a video switch signal CH-SEL based on a remote controlleroperation by the operator, for example, from outside, and selects thevideo signal of one intended channel according to the switch signalCH-SEL.

Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-40208

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

However, with the video interface device A disclosed in Patent Document1, although only one video signal is selected by the video selectioncircuit E, there are provided three input signal processing sections C-1to C-3 corresponding to the number of channels of the video signals B-1to B-3. The input signal processing sections C-1 to C-3 have the sameinternal configuration. As shown in FIG. 6 with respect to the inputsignal processing section C-1, for example, in a case where the videosignal B-1 includes a clock signal B-1C and a data signal B-1D, theinput signal processing section includes a receiver Ca and a PLL circuitCb for the clock signal B-1C, a receiver Cc for the data signal B-1D, aphase synchronization circuit Cd for phase synchronization between theclock signal B-1C and the data signal B-1D, a serial/parallel conversioncircuit Ce for performing a serial/parallel conversion on the videosignal from the phase synchronization circuit Cd, and an alignmentcircuit Cf for aligning the data train of the video signal from theconversion circuit Ce. Where the data signal B-1D includes a pluralityof data signals, a plurality of data signal receivers are required forthe data signals, and the phase synchronization circuit Cd, theserial/parallel conversion circuit Ce and the alignment circuit Cf eachrequire a large-scale configuration for accommodating the plurality ofdata signals.

Thus, with the conventional video interface device, it has been foundthat in the input signal processing sections (C-2 and C-3) other thanthe input signal processing section (e.g., C-1) for the video signalselected by the video selection circuit E, even if the video signals B-2and B-3 are not being input, components from the receivers Ca and Cc tothe alignment circuit Cf shown in FIG. 6 are in a stand-by operationwith a stand-by current therethrough, resulting in a large amount ofwasteful power consumption. The wasteful power consumption isparticularly significant where a data signal of each channel includes aplurality of data signals.

Moreover, the conventional video interface device has a very largecircuit scale as it requires the same number of input signal processingsections C-1 to C-3 as the number of channels of the input videosignals, as described above.

The present invention has been made based on this technical problem, anda first object of the present invention is to provide a signal receivingcircuit having a plurality of input channels, wherein the stand-byoperation is no longer necessary for input processing circuits of thosechannels where there is no signal input, thereby reducing the powerconsumption.

A second object of the present invention is to reduce a plurality ofinput processing circuits to a shared circuit to thereby reduce thecircuit area.

Means for Solving the Problems

In order to achieve the first object, the present invention provides aconfiguration where the presence/absence of a signal input from achannel is detected, so that it is possible to allow for an operation ofan input processing circuit corresponding to the channel for which thereis a signal input while stopping the stand-by operation of inputprocessing circuits corresponding to channels for which there is nosignal input.

In order to achieve the second object, the present invention provides aconfiguration where some input processing circuits are reduced to ashared circuit based on the fact that it is not necessary to provide aplurality of input processing circuits for all of a plurality ofchannels, i.e., some input processing circuits are not necessary, in theconfiguration as described above where the operation is allowed for onlyfor an input processing circuit corresponding to a channel for whichthere is a signal input.

Specifically, a signal receiving circuit of the present invention is asignal receiving circuit for receiving a signal separately for each of aplurality of channels, the signal receiving circuit including: aplurality of signal input detection circuits corresponding to theplurality of channels, each receiving a signal of the correspondingchannel for detecting a transition of the input signal and confirmingthat the signal of the corresponding channel is being received after thedetection of the transition of the signal to thereby detect an input ofthe signal of the corresponding channel; and one or more inputprocessing circuits each following a corresponding one of the signalinput detection circuits for receiving the signal of the channeldetected by the signal input detection circuit to perform apredetermined input signal process on the received signal.

In the signal receiving circuit of the present invention, the signal ofeach channel includes a clock signal and a data signal in apredetermined synchronized relationship with the clock signal.

In the signal receiving circuit of the present invention, the datasignal of each channel includes a plurality of data signals.

In the signal receiving circuit of the present invention, each of thesignal input detection circuits includes: a PLL circuit for receivingthe clock signal from the corresponding channel and outputting amultiplied clock signal obtained by multiplying the original clocksignal by a predetermined multiplier; a transition detection circuit forreceiving the original clock signal and detecting a transition of theoriginal clock signal to thereby output a transition detection signal;and a lock detection circuit, which is activated upon receiving thetransition detection signal of the transition detection circuit, fordetermining whether the PLL circuit has been locked based on theoriginal clock signal and the multiplied clock signal of the PLL circuitto thereby output a lock detection signal.

In the signal receiving circuit of the present invention, the PLLcircuit outputs the multiplied clock signal to the input processingcircuit.

In the signal receiving circuit of the present invention, the PLLcircuit is activated only after receiving the transition detectionsignal of the transition detection circuit.

In the signal receiving circuit of the present invention, the signalreceiving circuit includes a selection circuit following the signalinput detection circuits for selecting a signal of a channel of which aninput is detected by one of the signal input detection circuits, whereinthe input processing circuit is a 1-channel input processing circuitfollowing the selection circuit for performing a predetermined inputsignal process on the signal of the channel selected by the selectioncircuit.

In the signal receiving circuit of the present invention, the inputprocessing circuit at least includes a serial/parallel conversioncircuit for performing serial/parallel conversion of a signal.

A signal input detection circuit of the present invention is a signalinput detection circuit for detecting an input of a signal of apredetermined channel, wherein the signal input detection circuitreceives a signal of the channel for detecting a transition of the inputsignal and confirming that the signal of the corresponding channel isbeing received after the detection of the transition of the signal tothereby detect an input of the signal of the corresponding channel.

In the signal input detection circuit of the present invention, thesignal of the channel includes a clock signal and a data signal; and thesignal input detection circuit includes: a PLL circuit for receiving theclock signal included in the signal of the channel and outputting amultiplied clock signal obtained by multiplying the original clocksignal by a predetermined multiplier; a transition detection circuit forreceiving the original clock signal included in the signal of thechannel and detecting a transition of the original clock signal tothereby output a transition detection signal; and a lock detectioncircuit, which is activated upon receiving the transition detectionsignal of the transition detection circuit, for determining whether thePLL circuit has been locked based on the original clock signal and themultiplied clock signal of the PLL circuit to thereby output a lockdetection signal.

In the signal input detection circuit of the present invention, the PLLcircuit outputs the multiplied clock signal to outside the signal inputdetection circuit.

In the signal input detection circuit of the present invention, the PLLcircuit is activated only after receiving the transition detectionsignal of the transition detection circuit.

As described above, the signal receiving circuit of the presentinvention is a signal receiving circuit receiving a plurality ofchannels of input, wherein the signal input of each channel is detectedby a corresponding signal input detection circuit. Therefore, for eachchannel for which there is no signal input, the stand-by operation ofthe corresponding input processing circuit can be stopped based on theoutput of the corresponding signal input detection circuit. Thus, it ispossible to reduce the power consumption.

Particularly, with the signal receiving circuit of the presentinvention, in a case where there is only a signal input from one of aplurality of channels, the plurality of input processing circuitscorresponding to the plurality of channels can be reduced to a sharedinput processing circuit, thus eliminating the other input processingcircuits and achieving a significant reduction in the circuit area.

Moreover, with the input signal detection circuit of the presentinvention, the input signal detection circuit has a transition detectionfunction and a signal input confirmation function. Therefore, even ifnoise is superimposed on the signal of the channel or if the signalinput discontinues, the noise will not be detected erroneously as asignal input and the detection of the signal input will not becomeindeterminate, whereby it is possible to enhance the reliability of thesignal input detection.

EFFECTS OF THE INVENTION

As described above, the signal receiving circuit of the presentinvention is a signal receiving circuit receiving a plurality ofchannels of input, wherein the signal input is detected separately foreach channel. Therefore, it is possible to stop the stand-by operationof each input processing circuit corresponding to a channel for whichthere is no signal input. Thus, it is possible to reduce the powerconsumption.

Particularly, with the signal receiving circuit of the presentinvention, the plurality of input processing circuits corresponding tothe plurality of channels can be reduced to a shared input processingcircuit, thus achieving a significant reduction in the circuit area.

Moreover, with the input signal detection circuit of the presentinvention, even if noise is superimposed on the signal of the channel orif the signal input discontinues, the noise will not be detectederroneously as a signal input and the detection of the signal input willnot become indeterminate, whereby it is possible to enhance thereliability of the signal input detection.

BRIEF DESCRIPTION OF THE DRAWINGS

[FIG. 1] A circuit diagram showing a configuration of a signal receivingcircuit according to a first embodiment of the present invention.

[FIG. 2] A circuit diagram showing an internal configuration of an inputdetection circuit provided in the signal receiving circuit.

[FIG. 3] A circuit diagram showing a configuration of a signal receivingcircuit according to a second embodiment of the present invention.

[FIG. 4] A circuit diagram showing an internal configuration of an inputdetection circuit provided in the signal receiving circuit.

[FIG. 5] A diagram showing a configuration of an interface portion of aconventional signal receiving circuit.

[FIG. 6] A circuit diagram showing an example of an internalconfiguration of an input signal processing section provided in theinterface portion.

DESCRIPTION OF REFERENCE NUMERALS

-   -   1 Signal receiving circuit    -   2 a to 2 n. Input detection circuit (signal input detection        circuit)    -   3 Selection circuit    -   4 Phase synchronization circuit (input processing circuit)    -   5 Serial/parallel conversion circuit (input processing circuit)    -   6 Alignment circuit (input processing circuit)    -   S1 to SN Video signal    -   S1-c to SN-c Clock signal (original clock signal)    -   S1-d to SN-d Data signal    -   LOC-a to LOC-n Lock detection signal    -   10 Transition detection circuit    -   11 PLL circuit    -   11 a to 11 n Multiplied clock signal    -   12 Lock detection circuit    -   MOV-a Transition detection signal

BEST MODE FOR CARRYING OUT THE INVENTION

A signal receiving circuit according to an embodiment of the presentinvention will now be described with reference to the drawings.

First Embodiment

FIG. 1 shows a general configuration of a signal receiving circuitaccording to a first embodiment of the present invention.

A signal receiving circuit 1 shown in the figure receives N channels ofsignals S1, S2 . . . SN from N video signal supplying devices (notshown), e.g., a DVD player, a set top box (digital broadcast receiver),a personal computer, etc. Each of the channels of signals S1 to SNincludes a clock signal S1 c to SNc and a data signal S1 d, S2 d . . .SNd in a predetermined synchronized relationship with the correspondingclock signal. Each of the data signals Sid to SNd includes a pluralityof data signals.

The signal receiving circuit 1 includes therein N input detectioncircuits (signal input detection circuits) 2 a to 2 n corresponding tothe N channels of signals S1 to SN. The input detection circuits 2 a to2 n receive the clock signals S1 c to SNc of the signals S1 to SN of thecorresponding channels to each detect the transition of the clock signaland confirms that the clock signal continues to be input after thedetection of the transition thereof, thereby detecting the input of thesignal S1 to SN of the corresponding channel based on the transitiondetection and the signal input confirmation. The input detectioncircuits 2 a to 2 n have the same internal configuration, which will bediscussed below with reference to FIG. 2 using the input detectioncircuit 2 a as an example.

Referring to FIG. 2, the input detection circuit 2 a includes atransition detection circuit 10, a PLL circuit 11, and a lock detectioncircuit 12. The transition detection circuit 10 includes an integrationcircuit having a predetermined time constant, receiving thecorresponding clock signal S1-c input thereto. When the transition ofthe input signal is greater than or equal to the predetermined timeconstant, the transition detection circuit 10 determines that thetransition is that of the clock signal S1-c to output a transitiondetection signal MOV-a.

The PLL circuit 11 receives the original clock signal S1-c included inthe corresponding video signal S1 and multiplies the original clocksignal S1-c by a predetermined multiplier to output a multiplied clocksignal 11 c. Moreover, the lock detection circuit 12 is activated onlyafter receiving the transition detection signal MOV-c from thetransition detection circuit 10. The lock detection circuit 12 includestwo sets of counters (not shown), wherein one set receives the originalclock signal S1-c of the corresponding video signal S1 and the other setreceives the multiplied clock signal 11 c from the PLL circuit 11.Whether the PLL circuit 11 has been locked is determined based onwhether the output value of the last counter from each set matches theother after counting a predetermined number of clocks of the originalclock signal S1-c in the activated state, i.e., after receiving thetransition detection signal MOV-c from the transition detection circuit10. When lock is detected, a lock detection signal LOC-c is output, andthen the input of the video signal of the corresponding channel isdetected. The detection precision of the lock detection circuit 12 canbe enhanced by increasing the number of counters.

The rest of the configuration of the signal receiving circuit shown inFIG. 1 will now be described. Referring to FIG. 1, a selection circuit 3is provided following the n input detection circuits 2 a to 2 n. Theselection circuit 3 receives lock detection signals LOC-a to LOC-n fromthe N input detection circuits 2 a to 2 n. When the lock detectionsignal LOC-a to LOC-n is received from any of the input detectioncircuits 2 a to 2 n, i.e., when the input of the video signal of thecorresponding channel is detected, the selection circuit 3 selects theclock signal and the data signal in the video signal of the channel ofwhich an input is detected, and outputs the selected signals to thesubsequent section. Although not shown, if there are a plurality ofchannels of which the input is detected, a switch signal based on aremote controller operation by the operator is input to the selectioncircuit 3, based on which a video signal can be selected from among thechannels of video signals of which the input is detected.

Following the selection circuit 3, there are provided one set (onechannel) of, but not N sets of, a phase synchronization circuit 4, aserial/parallel conversion circuit 5 and an alignment circuit 6 in thisorder in the downstream direction as the input processing circuits. Thephase synchronization circuit 4 receives the clock signal CK and thedata signal D of the video signal selected by the selection circuit 3,and adjusts the phase between the signals CK and D so that the datasignal D can be latched desirably, for example. The serial/parallelconversion circuit 5 converts the clock signal SCK and the data signalQ, being serial data, from the phase synchronization circuit 4 intoparallel data of a plurality of bits. The alignment circuit 6 receivesthe clock signal SSCK and the data signal R from the serial/parallelconversion circuit 5 and detects a fixed pattern therein, e.g., apreamble pattern, to align the data train based on the fixed pattern.

Thus, in the present embodiment, there are N input detection circuits 2a to 2 n provided for N channels, and the input detection circuits 2 ato 2 n output the lock detection signals LOC-a to LOC-n when detectingthe corresponding video signals S1 to SN. When a lock detection signal(e.g., LOC-a) is received from one of the N input detection circuits 2 ato 2 n, the selection circuit 3 selects the clock signal S1-c and thedata signal S1-d included in the video signal S1 from the inputdetection circuit 2 a from which the lock detection signal is received,and outputs the selected signals to the subsequent section. The selectedand output signals, i.e., the clock signal S1-c and the data signalS1-d, are then subjected to a predetermined input process through thephase synchronization circuit 4, the serial/parallel conversion circuit5 and the alignment circuit 6.

Herein, the selection circuit 3 selects the video signal from one inputdetection circuit of which the video signal input is detected, fromamong the N input detection circuits 2 a to 2 n for N channels, and theselected video signal is successively subjected to input processesthrough one each of the phase synchronization circuit 4, theserial/parallel conversion circuit 5 and the alignment circuit 6. Thus,it is not necessary to provide N sets of these input processing circuits4, 5 and 6 for N channels. Therefore, as compared with a conventionalconfiguration, the stand-by current consumed by (N−1) sets of the inputprocessing circuits 4, 5 and 6 is saved. Thus, it is possible to reducethe power consumption.

Moreover, the input processing circuits 4, 5 and 6 can be shared by Nchannels and the number thereof can thus be reduced from N to one, thusallowing for a significant reduction in the circuit area.

While only one each of the input processing circuits 4, 5 and 6 isprovided as described above in the present embodiment, the presentinvention encompasses cases where N sets of the input processingcircuits 4, 5 and 6 are provided, separately for different channels,following the corresponding input detection circuits 2 a to 2 n. Then,with the configuration where the N input detection circuits 2 a to 2 noutput the lock detection signals LOC-a to LOC-n, respectively, if anyof the input detection circuits 2 a to 2 n does not output thecorresponding lock detection signal LOC-a to LOC-n, the stand-byoperation of the input processing circuits 4, 5 and 6 of thecorresponding channel can be stopped. In this case, although thearrangement of the input processing circuits 4, 5 and 6 requires as muchcircuit area as does a conventional configuration, the stand-by currentfor the inoperative input processing circuits 4, 5 and 6 can be saved.Thus, it is possible to reduce the power consumption.

A characteristic operation of the input detection circuits 2 a to 2 nwill now be described. In a case where the PLL circuit 11 and the lockdetection circuit 12 are not provided and only the transition detectioncircuit 10 is provided in the input detection circuit 2 a shown in FIG.2, if the clock signal S1-c is temporarily contaminated by noise, or thelike, for example, the transition of the noise, or the like, may beerroneously detected as the input of the clock signal. In the presentembodiment, however, if the transition detection circuit 10 erroneouslyoutputs the transition detection signal MOV-a, the following occurs.Although the lock detection circuit 12 is activated, the value of theinput signal (contaminating noise) multiplied by the PLL circuit 11 by apredetermined multiplier does not match that of the contaminating noisein the lock detection circuit 12, whereby the lock detection signalLOC-c will not be output, unlike when the clock signal S1-c is input(normal state). Therefore, the clock signal input is detected with ahigh precision.

If, for example, the transition detection circuit 10 is not provided inthe input detection circuit 2 a of FIG. 2, the lock detection circuit 12operates as a counter while the clock signal S1-c is being received, butmay transition into an indeterminate state when the input of the clocksignal S1-c discontinues, depending on how it discontinues. In thepresent embodiment, however, if the input of the clock signal S1-cdiscontinues while the lock detection circuit 12 is outputting the lockdetection signal LOC-c, the transition detection circuit 10 stopsoutputting the transition detection signal MOV-a to reset the lockdetection circuit 12, for example, thereby preventing the transitioninto an indeterminate state.

Therefore, with a configuration where the transition of the clock signalS1-c is detected by the transition detection circuit 10 and the lockdetection circuit 12 confirms that the video signal of the correspondingchannel (particularly, the clock signal) after the signal transition isdetected, as in the input detection circuit 2 a shown in FIG. 2, it ispossible to prevent the erroneous detection due to noise contaminationor the transition into an indeterminate state.

Second Embodiment

A second embodiment of the present invention will now be described withreference to FIGS. 3 and 4.

In the first embodiment, the clock signal input to the selection circuit3 is the original clock signal S1-a to S1-n included in the channel. Inthe present embodiment, it is instead the multiplied clock signal 11 ato 11 n, which has been multiplied by a predetermined multiplier by thePLL circuit 11 of the input detection circuit 2 a to 2 n.

Typically, in a data transmission standard, the transfer rate of a clocksignal differs from that of a data signal, and the clock signal needs tobe multiplied. From this point of view, in the present embodiment, themultiplied clock signals 11 a to 11 n of the PLL circuit 11 are used,thus sharing the PLL circuit 11 as a device for multiplying the clocksignal.

In the first and second embodiments, the transition detection signalMOV-a of the transition detection circuit 10 is output only to the lockdetection circuit 12 in the input detection circuit 2 a shown in FIGS. 2and 4. Alternatively, it may be output also to the PLL circuit 11 sothat the PLL circuit 11 will not be activated until the PLL circuit 11receives the transition detection signal MOV-a, whereby it is possibleto prevent the self-excited oscillation of the PLL circuit 11. Thus, afurther reduction in the power consumption can be expected.

Moreover, while the input detection circuits 2 a to 2 n detect the inputof a video signal by receiving the clock signals S1-c to SN-c includedin the video signals S1 to SN in the above description, the presentinvention is not limited to the configuration of the input detectioncircuits 2 a to 2 n receiving the clock signal. For example, where thevideo signal includes only the data signal but not the clock signal, thevideo signal (data signal) may be received, as opposed to theconfiguration of the input detection circuit of FIGS. 2 and 4. That is,the configuration of the input detection circuit is not limited to aparticular configuration as long as it detects the transition of theinput signal and confirms that the signal of the corresponding channelis being received after the detection of the transition of the inputsignal, thus detecting the input of the signal of the correspondingchannel.

INDUSTRIAL APPLICABILITY

As described above, with the signal receiving circuit of the presentinvention, the stand-by operation of any input processing circuit of achannel for which there is no signal input can be stopped, and moreovera plurality of input processing circuits can be reduced to a smallernumber of shared input processing circuits, thereby allowing for areduction in the power consumption or a reduction in the circuit area.Thus, the present invention is useful as a data transfer system, or thelike, for which a reduction in the power consumption or a reduction inthe circuit area is required.

Moreover, with the input signal detection circuit of the presentinvention, even if noise is superimposed on the signal of the channel orif the signal input discontinues, noise will not be detected erroneouslyas a signal input and the detection of the signal input will not becomeindeterminate, whereby it is possible to enhance the reliability of thesignal input detection. Thus, the present invention is useful as asignal detection circuit provided in a data transfer system, or thelike.

1. A signal receiving circuit for receiving a signal separately for eachof a plurality of channels, the signal receiving circuit comprising: aplurality of signal input detection circuits corresponding to theplurality of channels, each receiving a signal of the correspondingchannel for detecting a transition of the input signal and confirmingthat the signal of the corresponding channel is being received after thedetection of the transition of the signal to thereby detect an input ofthe signal of the corresponding channel; and one or more inputprocessing circuits each following a corresponding one of the signalinput detection circuits for receiving the signal of the channeldetected by the signal input detection circuit to perform apredetermined input signal process on the received signal.
 2. The signalreceiving circuit of claim 1, wherein the signal of each channelincludes a clock signal and a data signal in a predeterminedsynchronized relationship with the clock signal.
 3. The signal receivingcircuit of claim 2, wherein the data signal of each channel includes aplurality of data signals.
 4. The signal receiving circuit of claim 2,wherein each of the signal input detection circuits includes: a PLLcircuit for receiving the clock signal from the corresponding channeland outputting a multiplied clock signal obtained by multiplying theoriginal clock signal by a predetermined multiplier; a transitiondetection circuit for receiving the original clock signal and detectinga transition of the original clock signal to thereby output a transitiondetection signal; and a lock detection circuit, which is activated uponreceiving the transition detection signal of the transition detectioncircuit, for determining whether the PLL circuit has been locked basedon the original clock signal and the multiplied clock signal of the PLLcircuit to thereby output a lock detection signal.
 5. The signalreceiving circuit of claim 4, wherein the PLL circuit outputs themultiplied clock signal to the input processing circuit.
 6. The signalreceiving circuit of claim 4, wherein the PLL circuit is activated onlyafter receiving the transition detection signal of the transitiondetection circuit.
 7. The signal receiving circuit of claim 1, 2 and 4,comprising a selection circuit following the signal input detectioncircuits for selecting a signal of a channel of which an input isdetected by one of the signal input detection circuits, wherein theinput processing circuit is a 1-channel input processing circuitfollowing the selection circuit for performing a predetermined inputsignal process on the signal of the channel selected by the selectioncircuit.
 8. The signal receiving circuit of claim 1 or 7, wherein theinput processing circuit at least includes a serial/parallel conversioncircuit for performing serial/parallel conversion of a signal.
 9. Asignal input detection circuit for detecting an input of a signal of apredetermined channel, wherein the signal input detection circuitreceives a signal of the channel for detecting a transition of the inputsignal and confirming that the signal of the corresponding channel isbeing received after the detection of the transition of the signal tothereby detect an input of the signal of the corresponding channel. 10.The signal input detection circuit of claim 9, wherein: the signal ofthe channel includes a clock signal and a data signal; and the signalinput detection circuit includes: a PLL circuit for receiving the clocksignal included in the signal of the channel and outputting a multipliedclock signal obtained by multiplying the original clock signal by apredetermined multiplier; a transition detection circuit for receivingthe original clock signal included in the signal of the channel anddetecting a transition of the original clock signal to thereby output atransition detection signal; and a lock detection circuit, which isactivated upon receiving the transition detection signal of thetransition detection circuit, for determining whether the PLL circuithas been locked based on the original clock signal and the multipliedclock signal of the PLL circuit to thereby output a lock detectionsignal.
 11. The signal input detection circuit of claim 10, wherein thePLL circuit outputs the multiplied clock signal to outside the signalinput detection circuit.
 12. The signal input detection circuit of claim10, wherein the PLL circuit is activated only after receiving thetransition detection signal of the transition detection circuit.